Verilog & VLSI
Project Library

Delta-Sigma ADCs offer the most effective architecture for achieving highresolution, power-efficient analog-to-digital conversion. These ADCs generally have trade-offs between sampling rate and Effective Number of Bits (ENOB), where higher ENOBs are typically achieved at lower Nyquist sampling rates, and vice versa

FFT-based multiband spectrum sensing hardware for a full-duplex cognitive radio receiver with residual self-interference mitigation.

Fundamental butterfly unit implementing the Cooley–Tukey radix-2 DIT FFT algorithm.

Radix-2 DIT FFT module implementing the Cooley–Tukey divide-and-conquer algorithm for 4 points.

Pipeline-based 8-point FFT implementing the Cooley–Tukey radix-2 DIT algorithm with fixed-point precision.

Hierarchical 16-point FFT built using the Cooley–Tukey radix-2 DIT algorithm and optimized scaling.

High-precision 32-point FFT core implementing Cooley–Tukey radix-2 DIT recursion with fixed-point scaling.

Complete 64-point FFT system implementing the Cooley–Tukey radix-2 DIT divide-and-conquer algorithm.

High-precision multiplier based on the Posit number system with configurable bit-width.

Finite Impulse Response (FIR) filter implementation with 4 taps using fixed-point arithmetic.

Complex addition circuit for DSP applications.

Complex number multiplication module in Verilog.

Complex signed division module implemented in Verilog.

FIFO buffer design operating under a single clock domain.

Fully functional asynchronous FIFO with independent read and write clock domains, Gray-coded pointer synchronization, and safe full/empty detection.

Two flip-flop synchronizer for Gray-coded signals in clock domain crossing.

Pipelined 4-bit ripple carry adder with two pipeline stages for improved throughput.

16-bit carry select adder design with testbench.

Fast 2-bit carry look ahead adder implementation.

4-bit carry save adder design for parallel addition.

8-bit ripple carry adder circuit in Verilog.

Multi-bit ripple carry adder implementation.

Basic half adder circuit implemented in Verilog.

Testbench for half adder verification.

Single-bit full adder design in Verilog.

Multiplexer module used in carry save adder implementation.

Basic half subtractor design implemented in Verilog.

Single-bit full subtractor circuit in Verilog.

Unsigned fixed-point divider implemented in Verilog for Q-format arithmetic. Performs iterative division of two unsigned inputs using shift-and-subtract logic.

Signed fixed-point division module in Verilog supporting Q-format arithmetic. It performs signed division of two inputs with automatic sign handling and overflow detection.

Comparator module for checking equality, greater, and lesser conditions.

Digital logic mapped to IC 7420 (dual 4-input NAND gates).

Digital logic mapped to IC 7458 (AND-OR-INVERT gates).

Synchronous D flip flop design with clocked data storage.

Testbench for synchronous D flip flop validation.

Asynchronous D flip flop design with immediate reset behavior.

Testbench for asynchronous D flip flop validation.

JK flip flop implementation with toggling behavior.

Simple divide-by-2 clock divider circuit.

Comming soon - Collection of clock dividers for various ratios.

Converter module to transform binary numbers into Gray code.

Converter module to transform Gray code back into binary.

2-to-1 multiplexer implemented in Verilog.

Priority encoder circuit implemented in Verilog.

8-bit arithmetic shifter that preserves the sign bit during right shifts.

Universal logic gate implementation using NAND gates.